The invention relates generally to monolithic integrated circuits (ICs) and in particular to a buffer inverter amplifier that permits the design of ICs that operate at very low supply voltages as well as the higher voltages that are normally associated with such devices.
In the typical IC the well-known Darlington connected transistor amplifier is usually employed where very high current gain buffering is desired. If signal inversion is also desired, the output is taken from a load coupled to the commonly connected transistor collectors. In effect, the Darlington connected transistors act as a single transistor having a current gain approximating the product of the current gain of the individual devices.
While such circuits work very well, the supply voltage must be at least two V.sub.BE values plus one V.sub.SAT for a two-transistor configuration. For three transistors, the level must be greater than 3V.sub.BE +V.sub.SAT. Thus, over a reasonable temperature range the minimum supply voltage will be about 1.9 and 2.75 volts respectively for the and three transistor versions. In terms of battery operated circuits, this means that one cell operation is ruled out.
In the prior art, a close approach to the present invention is found in Jochems U.S. Pat. No. 2,874,232. Here the attempt was to fabricate a two-transistor monolithic amplifier device. In one embodiment, Jochems discloses an emitter follower stage directly coupled to a common emitter stage which includes a biasing network in its emitter. The biasing network complicates the circuit realization as a practical matter and is necessary to maintain the desired operating potentials.